Sunday, January 3, 2021

MIKUL 6218 Memory and VIA EXORbus board

I haven't spent much time working on my CMS 9639 SBC because, unlike the CMS 9619, it does not have any usable on-board RAM and does not include a monitor/debugger in ROM. Instead, it is designed to use an external memory board (which I don't have) on a back plane (which I now have) and boot OS-9 from a disk drive (which I don't have). What is nice about the device is the built-in memory manager which uses up to 1MiB of RAM. Unfortunately, EXORbus RAM cards are still prohibitively expensive on eBay and only have 16K to 64K of RAM capacity. Since the components would be far less than the price of those boards, I took a stab at designing a 1MiB SRAM board with a bonus additional I/O expansion.

I had just started to get components inserted into an EXORbus prototype board when I noticed the MIKUL 6218 Memory and VIA boards appearing on eBay at reasonable prices (<$45 shipped). Let's take a look at the board:

Click below for more details...

4 x 32 pin parallel memory sockets

The board has 4 x 32 pin parallel memory sockets connected to address lines up to A17, giving a total apparent maximum of (2^18)*4 or 1MiB RAM. So how does the board address all this RAM with only 16 address lines on the CPU and the bus (max 2^16 or 64K)? The board contains a 74ls273 octal (8-bit) register ("bank register") which acts as storage for the necessary high address bits. Just write a data byte representing the high address lines to a specific memory location, it is stored by the bank register, and the glue logic in the GALs selects the appropriate memory chip and bank. Super simple, but not compatible with the CMS 9639's scheme of memory manager with mapping RAM, task register, and extra address lines to address 4K of RAM for each running task.

3 x 6522 Versatile Interface Adapters (VIAs)

The 6522 VIA is basically an MC6840 PTM combined with a MC6821 PIA and a shift register. It is super 'versatile' and allows connection to many external devices, or prototyping projects that need digital I/O.

MIKUL 6218 Standard Implementation Details

The MIKUL board that I received contained an 8K SRAM ic, an 8K EEPROM, and a 64K(?) EPROM labeled TEMPMATE V3.013. Presumably, in an installed system, the VIAs are connected to temperature probes and TEMPMATE collects the temperatures and saves them to RAM or backs them up to EEPROM. I scanned the addresses on the board and came up with this basic memory map:

Unable to test
U7 6522 VIA EC8F
U1 6522 VIA EC7F
U2 6522 VIA EC6F
Unable to test EC5F



Note that the map does not include the bank switched addresses or memory addresses greater than $D7FF because I cannot currently access external addresses higher than that on any of the processor boards I have. The U6 64K EPROM is twice as large as the 32K assigned to it, so it is probably bank switched. Also, it is likely that this map is specific to the "TEMPMATE" implementation (see GAL markings below).

These are the programable ICs (GAL):

  • U16 (Marked "3002-R1")- Does the large block address decoding and controls the chip selects for the memory and U10.
  • U13 (Marked "3001-R0")- Interacts with the U11 bank register to generate the high addresses for the memory.
  • U10 (Marked "3003-R0")- Does the address decoding for the VIAs and bank register, and generates some control signals for the memory.

Basic W1, W2, W3, W4 Jumper Settings:

   . . . . .
 . . . . . ._.
   |     |
   . . . . .
  32K RAM
   . . . . .
 ._. . . . . .
         | |
   . . . . . 
   8K RAM
   . . . . .
       | |
 . . . . . . .
   . . . . . 

Anticipated Modifications

While the MIKUL 6218 would be a nice memory board on its own, I have slighly different needs than it was designed for. I have to adjust the logic on the board to get it to address the 2x 512K SRAM modules (that I already bought for this project) using the CMS 9639's A16-A19 address lines. For the CMS 9619, I think I could use the PIA to do the same sort of RAM bank selection on the finished card.

Overriding the U13 high address generation should be simple. I just have to remove the IC and strap the actual CPU address to the virtual address, leave the data from the bank latch open, and the high virtual addresses (A16 and A17) pulled high.

Overriding the U16 address decoder is going to be trickier. As you can see from the memory map, the system provides different sized address ranges for the memory chips, expecting an 8K SRAM in U5 starting at $0000 and a large EEPROM in U6 mapped from $2000 up to $BFFF. I think I will need to disable this IC and provide my own address decoding circuit.

Finally, I think I will inject the additional high addresses through a connector on a small daughterboard mounted to the U3 Memory socket.

More to come!

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