Saturday, October 29, 2016

Apple II+ 64K RAM Refresh and Addressing

I managed to add my modifications back to the Apple II logic board to get the 4164 RAM enabled. It seems to be working! However, I want to address all 64K of the RAM, not just 16K. To do that, I need to refresh the extra RAM rows, multiplex the RAM row and column address for the new RAM address pin, and make sure that row C of RAM stays enabled instead of selecting row C, D, or E. See the detailed plan of attack by clicking below.


After reviewing the problem of keeping the larger capacity RAM refreshed, it seemed that significant changes would have to be made to how the Apple II+ addresses the RAM to meet the refresh requirements during video scanning. It would basically have to mimic the Apple IIe addressing. However, after reading more about 4164 and 4264 DRAM refresh cycles, I realized that there is 64K DRAM that does not need all of rows refreshed. It is called "128cycle/2ms refresh". Since the Apple II+ video scanning / refresh already meets these requirements, I won't need to worry about refresh if I use this type of DRAM. I already bought some on eBay last week, and I hope it arrives in time.


The Apple II+ uses 3 rows of 8 RAM ICs. The rows are each addressed by the A14 and A15 address lines during CPU addressing and by the (HIRES TIME&PAGE 2) control lines during video scanning. Here is a table that shows how each row is addressed:
SelΦ0 MPUΦ1 Scanner

As you can see, the MPU only addresses RAM in the $0000 (A14'&A15') to $BFFF (A14'&A15) range, divided between the three rows. $C000 (A14&A15) and up are reserved for I/O and ROM. Video scanning only occurs on the first two rows of RAM.

So, the A14, A15 and (HIRES&PAGE 2) need to now control the extra address line (A7) of the 4264 RAM, rather than the row selection. It is necessary to 'multiplex' the row and column addresses to select the appropriate cell in the 4264 RAM. The Apple II+ does this with several 74LS153 4-to-1 multiplexers. I will need to add another one to multiplex the extra address line.

However, we still need to make sure that RAM is not enabled at $C000 and higher, when A14 and A15 addresses are both high. Fortunately, the Apple II+ already has that signal (A14&A15) connected from pin 6 of the H1 (74LS08 quad 2-input AND) chip to pin 6 of the F12 (74LS138 1-of-8 decoder) chip. So, I have to feed this new signal into the J1 (74LS257 2-to-1 multiplexer) chip to send a CAS' signal to row C RAM, unless A14&A15 are both high, and then select empty row D. I think this can be done by connecting the (A14&A15) signal to J1 pin 13 (disconnecting the existing A15 signal), keeping pin 14 always high and connecting pins 10 and 11 to ground (or a new bank select signal). This is a easy way to force the row C selection, unless (A14&A15) is high. I'm sure there is a much simpler way to do this, (there is, see below diagram) but I'm not exactly starting fresh and have to work with the ICs that are there. I have the added benefit of being able to add a signal later to select row E (ROW_E_SEL), if I have extra RAM and want a 128K Apple II+. I could also modify the A14&A15 signal later to select the 12K RAM in $D000-$FFFF range on command, like the Apple 16K RAM / Language card.

SelΦ0 MPUΦ1 Scanner
After starting to draw this out, I realized I can eliminate the 74LS257 at J1 and replace it with the new 74LS153, since only half of the 74LS257 is used by the Apple II, and the other half of the new 74LS153 can do the same thing.

Update: Below is a better drawing, correcting a few mistakes.

Note: Inputs are available to have another bank of 64K RAM on ROW E (ROWE_SEL), with an extra video screen (VID_RAM_SEL'), but they are not switchable (set to GND).

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