Saturday, January 19, 2013

Fun with Logic

While I was working on testing out different possible SPI speed settings and byte configurations, I started thinking more about ways to get my 1us read pulse while running at slower than a 1Mhz transfer speed. Then it hit me: by ANDing my data out (MOSI) to the SPI clock, I can get a read pulse half the duration of SPI data output!  At 500MHz, I have a perfect read pulse of 1us and 4us between the start of consecutive pulses!

(SCLK & MOSI) = perfect READ_PULSE

After doing some research, I realized I don't even need an extra chip to do this.  I can use a 74LS00 NAND gate for several bits of logic.  By connecting the two inputs of the NAND gate, I get the NOT gate I already needed.  To get an AND gate, I connect the SCLK and SPI output to each side of the NAND gate, then I connect the output back through a NAND gate with the two inputs connected.  NAND->NOT=AND.  It's not working yet, but I think it's close.

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